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Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Low Power Programmable Timing Control HubTM for P4TM processor
Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * PCIEX outputs cycle-cycle jitter < 125ps Output Features: * SATA outputs cycle-cycle jitter < 125ps * 2 - 0.7V push-pull differential CPU pairs * PCI outputs cycle-cycle jitter < 500ps * 5 - 0.7V push-pull differential PCIEX pairs * +/- 100ppm frequency accuracy on CPU, PCIEX and SATA clocks * 1 - 0.7V push-pull differential SATA pair +/- 100ppm frequency accuracy on USB clocks * 1 - 0.7V push-pull differential CPU/PCIEX selectable pair * * 1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX Features/Benefits: selectable pair * Supports tight ppm accuracy clocks for Serial-ATA and * 4 - PCI (33MHz) PCIEX * 2 - PCICLK_F, (33MHz) free-running * Supports programmable spread percentage and * 1 - USB, 48MHz frequency * 2 - REF, 14.318MHz * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning * PEREQ# pins to support PCIEX power management. * Low power differential clock outputs (No 50W resistor to GND needed) Recommended Application: Low Power CK410M Compliant Main Clock
Pin Configuration
VDDPCI GND PCICLK3 PCICLK4 *SELPCIEX0_LCD#PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 *SELLCD_27#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHzL DOTC_96MHzL FSLB/TEST_MODE 27FIX/LCD_SSCGT/PCIeT_L0 27SS/LCD_SSCGC/PCIeC_L0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2/REQ_SEL** PCI&PCIEX_STOP# CPU_STOP# REF1/FSLC/TEST_SEL REF0 GND X1 X2 VDDREF SDATA SCLK GND
Functionality Table
Bit 4 Bit 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 2 Bit 1 Bit 0 CPU FS LC FSLB FSLA MHz
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PCIEX MHz 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 100.75 101.75 102.74 103.74 104.74 105.74 106.73 107.73 108.73 109.73 110.72 111.72 112.72 113.72 114.71
PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
SATA MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
CPUT_L0 CPUC_L0
VDDCPU
CPUT_L1 CPUC_L1
VDD GNDA VDDA CPUITPT_L2/PCIeT_L6 CPUITPC_L2/PCIeC_L6 VDDPCIEX PEREQ1#/PCIeT_L5 PEREQ2#/PCIeC_L5
PCIeT_L1 PCIeC_L1
VDDPCIEX
PCIeT_L2 PCIeC_L2 PCIeT_L3 PCIeC_L3 SATACLKT_L SATACLKC_L
VDDPCIEX
PCIeT_L4 PCIeC_L4
GND
56-TSSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 271.99 274.66 277.33 279.99 282.66 285.33 287.99 269.33 271.99 274.66 277.33 279.99 282.66 285.33 287.99
ICS9LPR426A
115.71 33.33
1346-10/23/07 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Pin Description
PIN #
1 2 3 4 5 6 7 8 VDDPCI GND PCICLK3 PCICLK4 *SELPCIEX0_LCD#PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0
PIN NAME
TYPE
PWR PWR OUT OUT I/O PWR PWR I/O
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Free running PCI clock not affected by PCI_STOP#. SELLCD_27#: latched input to select pin functionality 1 = LCDCLK pair 0 = 27MHzSS/27MHzSS# pair Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm to GND needed. Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor to GND needed. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True clock of low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and SELLCD_27#. No 50ohm resistor to GND needed for differential outputs. 27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output / Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and SELLCD_27#. No 50ohm resistor to GND needed for differential outputs. True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) Power supply for PCI Express clocks, nominal 3.3V True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed) Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed) Power supply for PCI Express clocks, nominal 3.3V
9
*SELLCD_27#/PCICLK_F1
I/O
10 11 12 13 14 15
Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHzL DOTC_96MHzL
IN PWR I/O PWR OUT OUT
16
FSLB/TEST_MODE
IN
17
27FIX/LCD_SSCGT/PCIeT_L0
OUT
18 19 20 21 22 23 24 25 26 27 28
27SS/LCD_SSCGC/PCIeC_L0 PCIeT_L1 PCIeC_L1 VDDPCIEX PCIeT_L2 PCIeC_L2 PCIeT_L3 PCIeC_L3 SATACLKT_L SATACLKC_L VDDPCIEX
OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR
1346--10/23/07
2
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Pin Description (Continued)
PIN #
29 30 31 32 GND PCIeC_L4 PCIeT_L4 PEREQ2#/PCIeC_L5
PIN NAME
TYPE
PWR OUT OUT I/O
DESCRIPTION
Ground pin. Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of differential low power PCI Express output. No 50ohm resistor to GND needed. Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / True clock of differential low power PCI Express output. No 50ohm resistor to GND needed. Power supply for PCI Express clocks, nominal 3.3V Complement clock of differential pair CPU output. / Complement clock of differential PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed. True clock of differential pair CPU output. / True clock of differential PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed. 3.3V power for the PLL core. Ground pin for the PLL core. Power supply, nominal 3.3V Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs. No 50 ohm resistor to GND needed. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Stops all CPU clocks, except those set to be free running clocks Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PEREQ1#/PCIeT_L5 VDDPCIEX CPUITPC_L2/PCIeC_L6 CPUITPT_L2/PCIeT_L6 VDDA GNDA VDD CPUC_L1 CPUT_L1 VDDCPU CPUC_L0 CPUT_L0 GND SCLK SDATA VDDREF X2 X1 GND REF0 REF1/FSLC/TEST_SEL CPU_STOP# PCI&PCIEX_STOP# PCICLK2/REQ_SEL**
I/O PWR OUT OUT PWR PWR PWR OUT OUT PWR OUT OUT PWR IN I/O PWR OUT IN PWR OUT I/O IN IN I/O
1346--10/23/07
3
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
General Description
ICS9LPR426A is a low power CK410M-compliant clock specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR426A is driven with a 14.318MHz crystal.
Block Diagram
Fixed PLL X1 X2 SCLK SDATA FSLA FSLB FSLC PEREQ#(2:1) CPU_STOP# PCI/PCIEX_STOP# ITP_EN REQ_SEL TEST_SEL TEST_MODE Vtt_Pwr_GD/PD# PLL Array
Frequency Dividers
USB_48MHz
XTAL
REF(1:0) CPUCLKT (1:0) CPUCLKC (1:0) Programmable Frequency Divider Array CPUCLKT2_ITP/PCIEXT6 CPUCLKC2_ITP/PCIEXC6 PCICLK_F(1:0) STOP Logic PCICLK (5:2) PCIEXT (5:1) PCIEXC (5:1) SATACLKT SATACLKC 27FIX/LCD_SSCGT/PCIEX0T 27SS/LCD_SSCGC/PCIEX0C
Control Logic
M and N programming range
M 3 4 5 6 7 8 9 10 11 12 13 Minimum N 200 150 120 100 85 75 66 60 54 50 46 Maximum N 400 300 240 200 171 150 133 120 109 100 92 M 14 15 16 17 18 19 20 21 22 23 24 Minimum N 42 40 37 35 33 31 30 28 27 26 25 Maximum N 85 80 75 70 66 63 60 57 54 52 50
Yellow range is programming with more margin
1346--10/23/07
4
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Table 1: CPU PLL Spread Frequency Selection Table FS4 (B0b4)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FS3 (B0b3)
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS LC (B0b2)
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FSLB (B0b1)
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FSLA (B0b0)
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 271.99 274.66 277.33 279.99 282.66 285.33 287.99 269.33 271.99 274.66 277.33 279.99 282.66 285.33 287.99
Spread % +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center
1346--10/23/07
5
CPU PLL Spread Depends on PCI PLL Spread
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Table2: PCIEX PLL Spread and Frequency Selection Table FS4 (B19b4)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FS3 (B19b3)
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FSLC (B19b2)
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FSLB (B19b1)
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FSLA (B19b0)
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PCIEX MHz 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 99.75 100.00 101.75 102.74 103.74 104.74 105.74 106.73 107.73 108.73 109.73 110.72 111.72 112.72 113.72 114.71 115.71
Spread % +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center +/- 0.25 Center
1346--10/23/07
6
PCIEX PLL Spread Depends on PCI PLL Spread
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
Table3: SATA PLL Spread and Frequency Selection Table Bit 2 FS3 B22b2 (B31b6) (Hardwired Low = 0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 1 Bit 0 (Hardwired (Hardwired
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SATA MHz N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
Pin 17/18 MHz 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A* N/A*
Spread % 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center +/- 0.3 Center No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down
1346--10/23/07
7
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
SELPCIEX_LCD# and SELLCD_27# definition:
SELPCIEX_LCD# 0 0 1 1 SELLCD_27# 0 1 0 1 Pin #17/18 27MHzFixed/27MHz_SS pair LCD_SST/C pair PCIe0T/C PCIe0T/C SATA source PCI PLL SATA PLL SATA PLL SATA PLL
Table4: PCI PLL Spread and Frequency Selection Table Bit 3 Bit 4 Bit 2 (Hardwired (Hardwired Low = 0) (Hardwired Low = 0) Low = 0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FSLB (B22b1)
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FSLA (B22b0)
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
LCD/SATA MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
Spread % +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down +/- 0.25% Center +/- 0.5% Center +/- .3% Center 1% down
1346--10/23/07
8
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
General I2C serial interface information for the ICS9LPR426A How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P
1346--10/23/07
Not acknowledge stoP bit
9
Integrated Circuit Systems, Inc.
ICS9LPR426A Advance Information
I2C Table: Frequency Select Register Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROD SS_EN2 Reserved FS4 FS3 FSLC FSLB FSLA Control Function Reset on Demand PCI PLL Spread Enable Reserved Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW 0 Disable OFF 1 Enable ON PWD 0 1 X 0 0 Latch Latch Latch
See Table 1: Frequency Selection Table
I2C Table: Output Control Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Dot96Mhz I2C RB Reserved PCIEX PLL MNEN Reserved REF0 STRENGTH PCI/PCIEX_STOP# CPU PLL MNEN Control Function Output Control Select I2c readback from Reserved PCIEX PLL M/N Enable Reserved Strength Programming Stop all PCI and PCIEX clocks CPU PLL M/N Enable Type RW RW RW RW RW RW RW RW 0 Disable Shadow RAM Disable 1X Outputs Stopped Disable 1 Enable Active RAM Enable 2X Outputs Active Enable PWD 1 1 X 0 X 0 1 0
I2C Table: Output Control Register Byte 2 Name USB_48Mhz Bit 7 CPUCLK2_ITP / Bit 6 PCIEXT/C6 SATACLKT/C Bit 5 REF1 Bit 4 PCICLK5 Bit 3 PCICLK4 Bit 2 PCICLK3 Bit 1 PCICLK2 Bit 0 I2C Table: Output Control Register Byte 3 Name PCICLK1 Bit 7 PCICLK0 Bit 6 PCIEXT/C5 Bit 5 PCIEXT/C4 Bit 4 Reserved Bit 3 Reserved Bit 2 PCIEXT/C3 Bit 1 PCIEXT/C2 Bit 0 I2C Table: Output Control Register Name Byte 4 PCIEXT/C1 Bit 7 REF0 Bit 6 CPUCLK1 Bit 5 CPUCLK0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEL PCIEX_LCDCLK# PCIEXT/C0 Reserved Reserved
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
Control Function Output Control Output Control Output Control Output Control Reserved Reserved Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 X X 1 1
Control Function Output Control Output Control Output Control Output Control Selects PCIEX or LCD/27MHz on pins 17 and 18 Output Control Reserved Reserved
RW RW RW RW R RW RW RW
0 Disable Disable Disable Disable LCDCLK Disable -
1 Enable Enable Enable Enable PCIEX0 Enable -
PWD 1 1 1 1 latch 1 X X
1346--10/23/07
10
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ICS9LPR426A Advance Information
I2C Table: Output Control Register Byte 5 Name PCIEXT/C4 Bit 7 Reserved Bit 6 Reserved Bit 5 SATACLK Bit 4 PCIEXT/C3 Bit 3 PCIEXT/C2 Bit 2 PCIEXT/C1 Bit 1 PCIEXT/C0 Bit 0
Control Function RW RW RW RW RW RW RW RW
Allow assertion of PCI_STOP# or setting of PCI_STOP control bit in I2C register to stop PCIEX clocks.
0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running
1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable
PWD 0 X X 0 0 0 0 0
I2C Table: Amplitude Control Register Byte 6 Name Control Function Type Diff AMP RW CPU Differential output Amplitude Bit 7 Control Diff AMP RW Bit 6 Reserved Reserved RW Bit 5 Reserved Reserved RW Bit 4 Diff AMP RW DOT96 Differential output Amplitude Bit 3 Control Diff AMP RW Bit 2 Diff AMP SATACLK Differential output Amplitude RW Bit 1 Control Diff AMP RW Bit 0 I2C Table: Revision and Vendor ID Register Byte 7 Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 I2C Table: Byte Count Register Byte 8 Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0
0 00 = 700mV 10 = 800mV 00 = 700mV 10 = 800mV 00 = 700mV 10 = 800mV
1 01 = 900mV 11 = 1000mV 01 = 900mV 11 = 1000mV 01 = 900mV 11 = 1000mV
PWD 0 0 X X 0 0 0 0
Control Function Revision ID
VENDOR ID
Type R R R R R R R R
0 001 = ICS -
1 -
PWD 0 0 0 0 0 0 0 1
Control Function
Byte Count Programming b(7:0)
Type R R R RW RW RW RW RW
0
1
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
PWD 0 0 0 0 1 1 1 1
I2C Table: Watch Dog Timer Control Register Byte 9 Name Control Function HWD_EN Watchdog Hard Alarm Enable Bit 7 SWD_EN Watchdog Soft Alarm Enable Bit 6 WD Hard Status WD Hard Alarm Status Bit 5 WD Soft Status WD Soft Alarm Status Bit 4 WDTCtrl Watch Dog Alarm Time base Control Bit 3 HWD2 WD Hard Alarm Timer Bit 2 Bit 2 HWD1 WD Hard Alarm Timer Bit 1 Bit 1 HWD0 WD Hard Alarm Timer Bit 0 Bit 0
0 1 Type Disable Enable RW Enable Disable RW Normal Alarm R Normal Alarm R 1160ms Base 290ms Base RW RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = RW 2s. RW
PWD 0 0 X X 0 1 1 1
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I2C Table: WD Safe Frequency Control Register Byte 10 Name Control Function SWD2 WD Soft Alarm Timer Bit 2 Bit 7 SWD1 WD Soft Alarm Timer Bit 1 Bit 6 SWD0 WD Soft Alarm Timer Bit 0 Bit 5 WD SF4 Bit 4 WD SF3 Bit 3 Watch Dog Safe Freq Programming WD SF2 Bit 2 bits WD SF1 Bit 1 WD SF0 Bit 0 I2C Table: CPU PLL Frequency Control Register Byte 11 Name Control Function N Div2 N Divider Prog bit 2 Bit 7 N Div1 N Divider Prog bit 1 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Divider Programming M Div3 Bit 3 bit (5:0) M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0
Type 1 0 RW These bits represent X*290ms (or 1.16S) the watchdog timer RW waits before it goes to alarm mode. Default is 7 X 290ms = 2s. RW RW RW Writing to these bit will configure the safe frequency as RW Byte10 bit (4:0). RW RW
PWD 1 1 1 0 0 0 0 0
Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 24 x Ndiv(10:0)/Mdiv(5:0)
PWD X X X X X X X X
I2C Table: CPU PLL Frequency Control Register: Byte 12 Name Control Function Type N Div10 RW Bit 7 N Div9 RW Bit 6 N Div8 RW Bit 5 N Div7 N Divider Programming Byte12 bit(7:0) RW Bit 4 and Byte11 bit(7:6) N Div6 RW Bit 3 N Div5 RW Bit 2 N Div4 RW Bit 1 N Div3 RW Bit 0 I2C Table: PCI PLL Spread Spectrum Control Register Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 24 x Ndiv(10:0)/Mdiv(5:0)
PWD X X X X X X X X
0
1
Spread Spectrum Programming bit(7:0)
These Spread Spectrum bits in Byte 13 and 14 will program the spread percentage of PCI PLL
PWD X X X X X X X X
I2C Table: PCI PLL Spread Spectrum Control Register Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 X X X X X X X
Spread Spectrum Programming bit(14:8)
These Spread Spectrum bits in Byte 13 and 14 will program the spread percentage of PCI PLL
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I2C Table: PCIEX PLL Frequency Control Register Byte 15 Name Control Function N Div2 N Divider Prog bit 2 Bit 7 N Div1 N Divider Prog bit 1 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Divider Programming M Div3 Bit 3 bit (5:0) M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0
0 1 Type RW RW RW The decimal representation of M and N Divider in Byte 15 RW and 16 will configure the PCI PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = RW 24 x Ndiv(10:0)/Mdiv(5:0) RW RW RW
PWD X X X X X X X X
I2C Table: PCIEX PLL Frequency Control Register: 0 1 Byte 16 Name Control Function Type N Div10 RW Bit 7 N Div9 RW Bit 6 N Div8 RW The decimal representation of M and N Divider in Byte 15 Bit 5 N Divider Programming Byte16 bit(7:0) RW and 16 will configure the PCI PLL VCO frequency. Default at N Div7 Bit 4 power up = latch-in or Byte 0 Rom table. VCO Frequency = and Byte15 bit(7:6) N Div6 RW Bit 3 24 x Ndiv(10:0)/Mdiv(5:0) N Div5 RW Bit 2 N Div4 RW Bit 1 N Div3 RW Bit 0
PWD X X X X X X X X
Bytes 17,18 are reserved
I2C Table: PCIEX PLL Frequency Select Select Register Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved FS4 FS3 FSLC FSLB FSLA Control Function Reserved Reserved Reserved Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 Latch Latch Latch
See Table 2: PCIEX PLL Frequency Selection Table
I2C Table: Output Control Register Byte 20 Name Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1
Control Function
48Mhz
CPU_1 Load Control CPUCLK_2/ITP Reserved Reserved CPUCLK_0 RESET Sync
Strength Control
Free running Control IIC Load control Free-Running Controls Reserved Reserved Free Running Controls Reset Synchronization upon Reset (Byte 21)
Type RW RW RW RW RW RW RW RW
0 1x Free-Running Load Free-Running Free-Running Disable
1 2x Stoppable Do not Load Stoppable Stoppable Enable
PWD 0 0 0 0 1 1 0 0
Bit 0
I2C Table: Synchronization Control Register Byte 21 Name Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 1 1 1 1 1 1 1 1
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I2C Table: Output Control Register Byte 22 Name PCIEXT/C5 Bit 7 PCIEXT/C6 Bit 6 PCICLK_F1 Bit 5 PCICLK_F0 Bit 4 REF1 Bit 3 Reserved Bit 2 PCI PLL Freq. Select Bit 1 PCI PLL Freq. Select Bit 0
Control Function Free- Running Control Free- Running Control Free- Running Control Free- Running Control Strength Control Reserved Freq Select Bit 1 Freq Select Bit 0
Type RW RW RW RW RW RW RW RW
0 Free-Running Free-Running Free-Running Free-Running 1X -
1 Stoppable Stoppable Stoppable Stoppable 2X -
See Table 4: PCI PLL Frequency Selection Table
PWD 0 0 0 0 0 X 0 0
Bytes 23-27 are reserved
I2C Table: Programmable output divider Register Byte 28 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved CPUDiv3 CPUDiv2 CPUDiv1 CPUDiv0 Control Function Reserved Reserved Reserved Reserved CPU Divider Ratio Programming Bits for CPU PLL Type RW RW RW RW RW RW RW RW 0 0000:/2 0001:/3 0010:/5 0011:/7 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1 1100:/16 1101:/24 1110:/40 1111:/56 PWD X X X X X X X X
I2C Table: Programmable output divider Register Byte 29 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved PCIEXDiv3 PCIEXDiv2 PCIEXDiv1 PCIEXDiv0 Type RW RW RW RW RW PCIEX Divider Ratio Programming Bits RW for PCIEX PLL RW RW Control Function Reserved Reserved Reserved Reserved 0 0000:/2 0001:/3 0010:/5 0011:/7 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1 1100:/16 1101:/24 1110:/40 1111:/56 PWD X X X X X X X X
I2C Table: Programmable output divider Register Byte 30 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved PCIDiv3 PCIDiv2 PCIDiv1 PCIDiv0 Control Function Reserved Reserved Reserved Reserved PCI Divider Ratio Programming Bits Type RW RW RW RW RW RW RW RW 0 0000:/N/A 0001:/3 0010:/9 0011:/N/A 0100:/N/A 0101:/6 0110:/18 0111:/N/A 1000:/N/A 1001:/12 1010:/36 1011:/N/A 1 1100:/N/A 1101:/24 1110:/72 1111:/N/A PWD X X X X X X X X
I2C Table: PEREQ# Control Register Byte 31 Name SELLCD_27# Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 PEREQ2# Control Bit 3 PEREQ2# Control Bit 2 PEREQ1# Control Bit 1 PEREQ1# Control Bit 0
Control Function Select LCD or 27MHz for pins 17/18 Reserved Reserved Reserved PCIEX6 is controlled PCIEX1 is controlled PCIEX4 is controlled PCIEX0 is controlled
Type R RW RW RW RW RW RW RW
0 27MHz Not Controlled Not Controlled Not Controlled Not Controlled
1 LCDCLK Controlled Controlled Controlled Controlled
PWD latch X X X 0 0 0 0
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I2C Table: Skew programming Register Byte 32 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPUSkw3 CPUSkw2 CPUSkw1 CPUSkw0 CPUSkw3 CPUSkw2 CPUSkw1 CPUSkw0 Control Function CPUCLK0 Skew Control (ps) Type RW RW RW RW RW RW RW RW 0 0000:0 0001:100 0010:200 0011:300 0000:0 0001:100 0010:200 0011:300 0100:400 0101:500 0110:600 0111:700 0100:400 0101:500 0110:600 0111:700 1000:800 1001:900 1010:1000 1011:1100 1000:800 1001:900 1010:1000 1011:1100 1 1100:1200 1101:1300 1110:1400 1111:1500 1100:1200 1101:1300 1110:1400 1111:1500 PWD 0 0 0 0 0 0 0 0
CPUCLK1 Skew Control (ps)
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Absolute Maximum Rating
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection HBM
1
SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot
CONDITIONS -
MIN
TYP
MAX VDD + 0.5V
UNITS V V
Notes 1 1 1 1 1 1
GND - 0.5 -65 0 2000
VDD + 0.5V 150 70 115
C
C C V
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FS VIL_FS IDD3.3OP IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization Modulation Frequency Tdrive_PD Tfall_PD Trise_PD SMBus Voltage VDD TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of 2.7 CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% Full Active, CL = Full load; all outputs driven all diff pairs driven VDD = 3.3 V MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 175 175 2 14.31818 7 5 6 5 1.8 30 33 300 5 5 5.5 0.4 4 1000 300 VDD + 0.3 0.35 350 400 70 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns Notes 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
1 2
Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
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AC Electrical Characteristics - (CPU, PCIEX, SATACLK, DOT96Mhz)
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC Skew
1 2 3
SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJC2C SRCJC2C DOTJC2C CPUSKEW10 CPUSKEW20 SRCSKEW
CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement
MIN 2.5 2.5
MAX 8 8 20 1150
UNITS V/ns V/ns % mV mV mV
NOTES 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1
-300 300 300 45 550 140 55 85 125 250 100 150 TBD
mV mV % ps ps ps ps ps ps
*TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1 3
SYMBOL RDSP VOH VOL IOH IOL tslewr/f tr tf dt1 tskew tjcyc-cyc
CONDITIONS* VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4
TYP
MAX 55 0.55
UNITS V V mA mA mA mA V/ns ns ns % ps ps
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 0.5 0.5 45 4 2 2 55 250 500
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. Spread Spectrum is off
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Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER Long Accuracy Clock period Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1
SYMBOL ppm Tperiod RDSP VOH VOL IOH IOL tslewr/f tslewr/f_USB tr tf tr_USB tf_USB dt1 tskew tjcyc-cyc
CONDITIONS* see Tperiod min-max values 48.00MHz output nominal VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate USB48 Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN -100 20.8313 12 2.4
TYP
MAX 100 20.8354 55 0.55
UNITS ppm ns V V mA mA mA mA V/ns V/ns ns ns ns ns % ps ps
NOTES 1,2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 1 0.5 0.5 1 1 45 4 2 2 2 2 2 55 250 500
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF-14.318MHz
PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Skew Duty Cycle Jitter
1 2
SYMBOL ppm Tperiod VOH VOL IOH IOL tslewr/f tr1 tf1 tsk1 dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, @MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VOL
MIN -300 69.8270 2.4
TYP
MAX 300 69.8550 0.4
UNITS ppm ns V V mA mA V/ns ns ns ps % ps
Notes 1,2 2 1 1 1 1 1 1 1 1 1 1
-29 29 1 1 1 45
-23 27 4 2 2 500 55 1000
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
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Test Clarification Table
Comments
FSLC/ TEST_SEL HW PIN
HW
FSLB/ TEST_MODE HW PIN
<2.0V Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input
X
OUTPUT NORMAL
>2.0V
0
HI-Z
>2.0V
1
REF/N
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ICS9LPR426A Advance Information
N
c
L
E1 INDEX AREA
E
12
D
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 MAX .555
-Ce
b SEA TING PLANE
56
10-0039
aaa C
Reference Doc.: JEDEC Publication 95, M O-153
Ordering Information
ICS9LPR426AGLF-T
Example:
ICS XXXX A G LF- T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator Device Type Prefix ICS = Standard Device
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ICS9LPR426A Advance Information
Revision History
Rev. 0.1 0.2 0.3 0.4 0.5 0.6 Issue Date Description 05/09/07 Initial Release 06/04/07 Updated SMBUS 1. Updated Output Features. 06/22/07 2. Updated Block Diagram 08/21/07 Added Test Clarification Table. 09/14/07 Updated Electrical Characteristics. 10/23/07 Added Programming Range Table Page # Various 1, 4 19 16 4
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